1. Field of Invention
The present invention relates to a method for fabricating semiconductor devices. More particularly, the present invention relates to a method for fabricating a crown-shaped dynamic random access memory (DRAM) capacitor.
2. Description of Related Art
DRAMs are now extensively used in all kinds of integrated circuit devices. They have become an indispensable element in the electronic industries. FIG. 1 illustrates a circuit diagram of a memory unit of a DRAM device. As shown in FIG. 1, the memory unit comprises a pass transistor T and a storage capacitor C. The source terminal of the pass transistor T is connected to a bit line (BL) and the drain terminal is connected to a storage electrode 6 of the storage capacitor C. The gate terminal of the pass transistor T is connected to a word line (WL). The opposed electrode 8 of the storage capacitor C is connected to a fixed voltage source. Between the storage electrode 6 and the opposed electrode 8, there is a dielectric layer 7. Those who are familiar with the art of semiconductor manufacturing may know that the capacitor C functions as a storage place for digital data. Therefore, the capacitor C should have a sufficiently large capacitance to avoid rapid data loss.
In the fabrication of conventional DRAMs with a memory capacity up to about 1 MB, a two dimensional capacitor device, generally known as a planar-type capacitor, is often employed for storing digital data. In a conventional planar-type DRAM capacitor, as shown in FIG. 2, a silicon substrate 10 is provided first. Then, a field oxide layer 11 is formed on the substrate 10 to define the active regions. Next, a gate oxide layer 12, a gate layer 13 and source/drain regions 14 are sequentially formed above the substrate 10, constituting a pass transistor T. In a subsequent step, a dielectric layer 7 and a conducting layer 8 are sequentially formed over portions of the substrate 10 near the drain terminal. The region 6 where the dielectric layer 7 and the conducting layer 8 overlap the substrate 10 forms a storage capacitor C. For the planar-type capacitor structure described, a relatively large surface area is required to form a storage capacitor C that has sufficient capacitance. Hence, this design is unsuitable for DRAM devices with high-level integration.
In general, highly integrated DRAMs, for example, those larger than about 4 MB memory capacity, require a three-dimensional capacitor structure, such as a stack-type or a trench-type structure, for the capacitor devices.
FIG. 3 is a cross-sectional view of a conventional stack-type capacitor structure. As shown in FIG. 3, a field oxide layer 11, a gate oxide layer 12, a gate layer 13 and source/drain regions 14 are sequentially formed on a substrate 10, which constitute a pass transistor T. Thereafter, an insulating layer 15 is formed on the substrate 10, then a contact opening 14 is etched out exposing portions of the source/drain region 14. Subsequently, a polysilicon layer 6 (serving as the storage electrode), a dielectric layer 7 and a conducting layer 8 (serving as the opposed electrode) are sequentially formed over the contact opening 14. This produces a stack-type DRAM capacitor memory unit. The above stack-type capacitor structure is capable of supplying sufficiently large capacitance with relatively good device reliability. However, for higher level of integration, such as a 64 MB or larger storage capacity DRAM, a simple stack-type capacitor is insufficient.
Another technique for increasing the capacitance is to produce a trench-type capacitor. FIG. 4 is a cross-sectional view of a conventional trench-type capacitor structure. As shown in FIG. 4, processes very similar to those used in the fabrication of a stack-type capacitor are performed first to produce a pass transistor T on a silicon substrate 10. The pass transistor T includes a gate oxide layer 12, a gate layer 13 and source/drain regions 14. Thereafter, a deep trench is formed by etching the substrate 10 near the drain terminal 14, and a storage capacitor C is formed inside the trench region. The storage capacitor C is formed on the sidewalls of the trench. The capacitor C comprises a storage electrode 6, a dielectric layer 7 and a polysilicon opposed electrode 8. The above trench-type capacitor has a larger surface area of the electrode and hence large capacitance. However, etching the substrate 10 to form a trench may cause some damages to the crystal lattice structure, and more current may leak, thereby affecting operation of the device. Furthermore, as an aspect ratio of the trench increases, the etching rate will correspondingly decrease; therefore, fabrication becomes more difficult and time consuming.
In light of the foregoing, there is a need for an improved method for fabricating a DRAM capacitor with larger capacitance.